The design of electrically-differential MEMS microphones requires minimal (ideally zero) variation in the DC output magnitudes of the positive and negative charge pumps (CPs) to ensure that the acoustic signals generated by each microphone are truly differential. Although careful design can keep this difference low, dissimilarities in layout can produce leakage paths or other loss mechanisms in each pump that can increase the separation between the efficiency of the positive and negative CPs, which in turn make the voltage difference between both pumps worse. These factors are amplified as the charge pumps are evaluated across process, frequency, etc.
Prior art describes the use of individual charge pump cells to create positive and negative charge pumps as illustrated in FIG. 1. Specifically, FIG. 1 shows schematic representations of a positive charge pump cell 102 and a negative charge pump cell 104. In some embodiments, the charge pump cells can be cascaded to form a larger charge pump to provide a larger DC output voltage thus increasing the DC output voltage. FIG. 1 further shows a multi-stage positive charge pump 106 and a multi-stage negative charge pump 108. The output voltage of the multi-stage positive charge pump 106 can be determined based on the equation: OUT+=[ηSTAGE+*(VREFP)(NTOTAL_STAGES)]+VIN, where our is the positive output voltage, VIN is the input voltage, VREFP is a reference voltage, NTOTAL_STAGES is the total number of charge pump stages and ηSTAGE+ is the efficiency of the positive charge pump. Similarly, the output voltage of the multi-stage negative charge pump 108 can be determined based on the equation: OUT−=−VIN−[ηSTAGE−*(VREFN)(NTOTAL_STAGES)], where OUT is the negative input voltage and ηSTAGE− is the efficiency of the negative charge pump.
FIGS. 2 and 3 show differences in the most basic layouts for a positive charge pump cell (FIG. 2) and a negative charge pump cell (FIG. 3). The positive charge pump cell of FIG. 2 includes a p-type substrate 202. An n-type well 204 is formed within the p-type substrate 202 and includes two n+ doped regions 206 and 208. The n-well 204 is connected to VOUT+ through the n+ doped regions 206 and 208. An optional second n-well region 222 can be placed in the n-type well 204. Within the n-well regions 204 or 222, p-type metal-oxide-semiconductor (PMOS) transistors are formed by the p-type region 226. The gates and drains of the PMOS transistors are connected to nodes A and B according to the charge pump cell 102 while the sources and bulks of the PMOS transistors are connected to VOUT+. A p-type well 210 is formed in the n-type well 204 and includes two p+ regions 212 and 214. The p-well 210 is connected to VIN+. An optional second p-well region 216 can be placed in the p-type well 210. Within the p-well regions 210 or 216, n-type metal-oxide-semiconductor (NMOS) transistors are formed by the n-type regions 220. The gates and drains of the NMOS transistors are connected to nodes A and B according to the charge pump cell 102 while the sources and bulks of the NMOS transistors are connected to VIN+.
The negative charge pump cell of FIG. 3 includes a p-type substrate 302. An n-type well 304 is formed within the p-type substrate 302 and includes two n+ doped regions 306 and 308. The n-well 304 is connected to GND through the n+ doped regions 306 and 308. A p-type region 310 is formed within the n-well 304. The p-type region 310 is connected to VOUT− through the p+ doped region 312. A second n-well region 322 is formed within the p-type region 310. Within the n-well region 322, PMOS transistors are formed by the p-type region 326. The gates and drains of the PMOS transistors are connected to nodes A and B according to the charge pump cell 104 while the sources of the PMOS transistors are connected to VIN−. An optional second p-well region 316 can be placed in the p-type well 310. Within the p-well regions 310 or 316 NMOS transistors are formed by the n-type regions 320. The gates and drains of the NMOS transistors are connected to nodes A and B according to the charge pump cell 104 while the sources of the NMOS transistors are connected to VOUT−.
As noted above, the differences in layouts of the previously known positive and negative charge pumps can produce leakage paths or other loss mechanisms in each pump that can increase the separation between the efficiency of the positive and negative CPs. The efficiency difference can in turn make the voltage difference between the two charge pumps larger. Improvements to charge pumps in MEMS microphones to reduce or eliminate differences in the DC output magnitude from CPs would be beneficial.